Method of, and apparatus for, optimization of dataflow hardware
US8689156B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2013 |
| Grant date | Apr 1, 2014 |
| Priority date | — |
| Expiry date | Feb 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating a hardware design for a pipelined parallel stream processor. The method includes defining a processing operation designating processes to be implemented in hardware as part of said pipelined parallel stream processor and defining a graph representing said processing operation as a parallel structure in the time domain as a function of clock cycles. The method also includes defining the at least one data path and associated latencies of said graph as a set of algebraic linear inequalities, collectively solving the set of linear inequalities for the entire graph, optimizing the at least one data path in the graph using the solved linear inequalities to produce an optimized graph, and utilizing the optimized graph to define an optimized hardware design for implementation in hardware as the pipelined parallel stream processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.