Thin film transistor array substrate and method for fabricating the same
US8692250B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2008 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Oct 8, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/58
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a TFT array substrate including the following steps is provided. A substrate having a pixel region and a photosensitive region is provided. A first patterned conductive layer is formed on the substrate, wherein the first patterned conductive layer includes a gate electrode disposed in the pixel region and a first electrode disposed in the photosensitive region, and a photosensitive dielectric layer is formed on the first electrode. A gate insulation layer is formed to cover the gate electrode, the photosensitive dielectric layer and the first electrode. A patterned semiconductor layer is formed on the gate insulation layer above the gate electrode. A source electrode and a drain electrode are formed on the patterned semiconductor layer at two sides of the gate electrode, wherein the gate electrode, the source electrode, and the drain electrode constitute a TFT. A second electrode is formed on the photosensitive dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.