Circuit substrate structure
US8692266B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2013 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Apr 2, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.