Semiconductor device
US8692336B2 · kind B2 · utility
6Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2012 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Mar 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/991
Abstract
A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.