Latched comparator circuitry
US8692582B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2012 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Jan 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/249
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Integrated circuits having analog-to-digital converters are provided. Analog-to-digital converters may contain latched comparators. A latched comparator may include inputs configured to receive a differential input voltage signal, a differential reference voltage signal, and a clock signal. The comparator may include a preamplifier, a latching circuit, a level shifter, and a flip-flop coupled in series. The preamplifier may include large input transistors for minimizing offset, stacked tail transistors, and diode-connected load transistors for minimizing kickback noise. The preamplifier may be used to generate amplified voltage signals. The latching circuit may include a first pair of cross-coupled pull-down transistors, a second pair of cross-coupled pull-up transistors, and precharge transistors. The precharge transistors may serve to precharge the latch output to a predetermined voltage level during a first clock phase, whereas the first and second transistor pairs may serve to perform exponential regeneration on the amplified voltage signals during a second clock phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.