Power stage
US8692591B2 · kind B2 · utility
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44References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 26, 2012 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Oct 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.