Interpolative divider linearity enhancement techniques
US8692599B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2012 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Aug 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flexible clock synthesizer technique includes generating a phase interpolator calibration signal to adjust a phase interpolator output signal generated by a phase interpolator of an interpolative divider. The phase interpolator is responsive to a phase interpolator control code and an output signal of a fractional-N divider of the interpolative divider. The phase interpolator calibration signal is based on an error signal indicative of a phase interpolator error. The error signal may indicate a phase relationship between a reference clock signal and a feedback clock signal of a PLL. The interpolative divider may be coupled in a feedback path of the PLL. The PLL may receive a reference clock signal and the feedback clock signal may be an adjusted phase interpolator output signal. The phase interpolator calibration signal may be a phase interpolator offset code corresponding to the phase interpolator control code or a phase interpolator gain signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.