Memory array
US8693243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2011 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | May 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.