Synchronous global controller for enhanced pipelining
US8693279B2 · kind B2 · utility
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33References
20Claims
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Key dates
| Filing date | Feb 18, 2013 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Feb 18, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a memory block and a controller. The controller is adapted to skew a pre-charge signal for a bit line of the memory block. The controller can skew the pre-charge signal during a read operation or a write operation. The system can also include a sense amplifier in communication with a bit line of the memory block, and the sense amplifier can automatically shut off after indicating a sensed data state for the bit line. The controller may be a global controller or a local controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.