Receiver, receiver circuits, and methods for providing an interference-reduced signal
US8693971B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2012 |
| Grant date | Apr 8, 2014 |
| Priority date | — |
| Expiry date | Dec 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B7/0639
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A receiver is configured to receive a receive signal including a plurality of signal components, each signal component indicating a channel of an antenna port and an associated scrambling sequence, wherein a first one of the channels indicated by a first one of the signal components which is based on a first scrambling sequence is allocated to the receiver for data reception and a second one of the channels indicated by a second one of the signal components which is based on a second scrambling sequence different from the first scrambling sequence is interfering with the allocated channel. The receiver includes an interference reduction unit configured to combine an estimate of the first one of the signal components and an estimate of the second one of the signal components to provide an interference-reduced signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.