Methods of manufacturing three dimensional semiconductor memory devices using sub-plates
US8697498B2 · kind B2 · utility
14Cited by
1References
10Claims
0Family size
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Key dates
| Filing date | Oct 28, 2011 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Jan 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a Three Dimensional (3D) semiconductor memory device can be provided by forming at least one trench in a plate stack structure to divide the plate stack structure into a plurality of sub-plate stack structures between forming a plurality of vertical active patterns in the plate stack structure and forming pads of a stepped structure from the plate stack structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.