Semiconductor device, and test method for same
US8698140B2 · kind B2 · utility
3Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2010 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | May 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.