Integrated circuit layout having mixed track standard cell
US8698205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2012 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Jun 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/974
Abstract
An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.