Delay time control circuit and control method thereof
US8698529B2 · kind B2 · utility
2Cited by
2References
13Claims
0Family size
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Key dates
| Filing date | Feb 4, 2013 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Feb 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00065
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay time control circuit is provided which includes a delay locked loop generating a second clock signal delayed by a predetermined time in response to a first clock signal; a plurality of delay circuits each receiving the first and second clock signals and outputting third and fourth clock signals in response to first and second digital clock signals; and a feedback control unit receiving the third and fourth clock signals to detect a delay time and generating the first and second digital control signals for compensating the detected delay time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.