Resonator circuit and amplifier circuit
US8698570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2011 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Jun 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G3/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A passive frequency divider in a CMOS process. More specifically, an electrical distributed parametric oscillator to realize a passive CMOS frequency divider with low phase noise. Instead of using active devices, which are the main sources of noise and power consumption, an oscillation at half of the input frequency is sustained by the parametric process based on nonlinear interaction with the input signal. For example, one embodiment is a 20 GHz frequency divider utilizing a CMOS varactor and made in a 0.13 μm CMOS process. In this embodiment: (i) without any dc power consumption, 600 mV differential output amplitude can be achieved for an input amplitude of 600 mV; and (ii) the input frequency ranged from 18.5 GHz to 23.5 GHz with varactor tuning. In this embodiment, the output phase noise is almost 6 dB lower than that of the input signal for all offset frequencies up to 1 MHz. Also, a resonant parametric amplifier with a low noise figure (NF) by exploiting the noise squeezing effect. Noise squeezing occurs through the phase-sensitive amplification process and suppresses one of two quadrature components in input noise. When the input signal is only in the direction of the non-su…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.