Patent · US Active

Memory circuitry with dynamic power control

US8699291B1 · kind B1 · utility

6Cited by

5References

19Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Chin-Ghee Ch'ng · Air Itam, MY
Wei Yee Koay · Kampung Bukit Kechil, MY
Boon Jin Ang · Butterworth, MY

Key dates

Filing date	Mar 8, 2012
Grant date	Apr 15, 2014
Priority date	—
Expiry date	May 23, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG11C5/148
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Circuits and techniques for operating a memory circuit are disclosed. A disclosed circuit includes a memory circuit and a sleep circuit with an output terminal coupled to the memory circuit. The sleep circuit is operable to receive a control signal and further operable to place the memory circuit in different modes of operation. The memory circuit may be placed in either a first mode of operation, a second mode of operation or a third mode of operation based at least partly on the control signal. An input terminal of the sleep circuit is coupled to an output terminal of the control circuit. The control circuit is operable to receive an enable signal and is operable to supply the control signal to the sleep circuit at first, second and third voltage levels during the first, second and third modes of operation, respectively, based on the enable signal and a clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.