Dutycycle adjustment to improve efficiency of a digital RF-PA
US8699619B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2010 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Dec 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplification unit reduces a duty cycle of a digital signal at a carrier radio frequency to optimize the efficiency of the RF power amplifier that amplifies the reduced duty cycle signal. An exemplary amplification unit includes a duty cycle controller and a digital power amplifier. A delay unit in the duty cycle controller applies a delay to an input digital signal at the carrier radio frequency to generate a delayed signal at the carrier radio frequency. A logic gate in the duty cycle controller logically combines the input digital signal with the delayed signal to generate a modified digital signal at the carrier radio frequency, where the modified input digital signal has a reduced duty cycle relative to that of the input digital signal. Amplifying the modified digital signal in the digital RF power amplifier generates an amplified analog signal at the carrier radio frequency while improving amplifier efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.