Processor configured for operation with multiple operation codes per instruction
US8700886B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2007 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Jun 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30156
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor configured to operate with multiple operation codes for each of a plurality of instructions comprises memory circuitry and processing circuitry coupled to the memory circuitry. The processing circuitry is configured to decode a first operation code to produce a given one of the instructions and to decode a second operation code different than the first operation code to also produce the given instruction. Thus, the same instruction is produced for execution by the processing circuitry regardless of whether the first operation code or the second operation code is decoded. The assignment of multiple operation codes to a given instruction may occur in conjunction with the design of the processor, and dynamic selection of a particular one of those operation codes may be performed in conjunction with assembly of code for execution by the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.