Method and system for repartitioning a hierarchical circuit design
US8701059B2 · kind B2 · utility
1Cited by
29References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2013 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Mar 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.