Systems and methods for optimizing allocation of hardware resources to control logic in parallel pipelined hardware
US8701069B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 21, 2012 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Nov 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of utilizing high level synthesis to automatically configure control logic of a hardware design for a pipelined parallel stream processor includes obtaining a scheduled graph representing a processing operation in the time domain as a function of clock cycles. The graph includes a data path to be implemented in hardware as part of the stream processor, an input, an output, functional objects, and parallel branches to enable data values to be streamed therethrough from the input to the output as a function of increasing clock cycle. The functional objects are grouped based upon having a cycle position dependent upon common factors. Common control logic elements are allocated to groups of functional objects. The graph and allocated control logic is used to define a hardware design for the pipelined parallel stream processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.