Dual speed readout integrated circuit for high spatial and temporal resolution applications
US8704144B2 · kind B2 · utility
6Cited by
8References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2011 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Jan 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/778
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A dual speed Read-Out Integrated Circuit employs a native pixel array with associated high resolution integration circuits for each pixel and a superpixel array created within the native pixel array by combination of native pixels for charge sharing integration in reduced resolution integration circuits simultaneously with the integration of the high resolution integration circuits. Switching control for readout of the high resolution integration circuits is accomplished at a first frame rate and switching control for readout of the reduced resolution integration circuits is accomplished at a second higher frame rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.