Three dimensional semiconductor memory device and method for fabricating the same
US8704293B2 · kind B2 · utility
14Cited by
0References
20Claims
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Key dates
| Filing date | Sep 13, 2011 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Mar 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.