High linearity mixer using a 33% duty cycle clock for unwanted harmonic suppression
US8704582B2 · kind B2 · utility
7Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2012 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Oct 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A mixer circuit is disclosed. The mixer circuit comprises a plurality of mixer elements, wherein there are non-overlapping clock signals provided to the plurality of mixer elements which have a duty cycle of 33⅓ percent. Outputs signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. The third-order harmonic of the mixer is eliminated by using mixer which uses voltage sampling on non-overlapping clocks and thereby achieves high linearity. The mixer circuit is further expanded to remove the I-Q image and even order harmonics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.