High-voltage tolerant biasing arrangement using low-voltage devices

US8704591B1 · kind B1 · utility

Assignee

• LSI · US

Inventors

• Pankaj Kumar · Barwala, IN
• Pramod Elamannu Parameswaran · Savanuru, IN
• Vani Deshpande · Bengaluru, IN
• Makeshwar Kothandaraman · Whitehall, US

Key dates

• Filing date: Nov 8, 2012
• Grant date: Apr 22, 2014
• Expiry date: Nov 8, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G05F3/24
• WIPO field: Control
• WIPO sector: Instruments

Abstract

A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly.