Semiconductor device having dummy bit lines wider than bit lines
US8705261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2012 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Jul 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.