Three-dimensional multi-bit non-volatile memory and method for manufacturing the same

US8705274B2 · kind B2 · utility

Assignee

• INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Ming Liu · Beijing, CN
• Chenxi Zhu · Fairfax, US
• Zongliang Huo · 红钢城街道, CN
• Feng Yan · Beijing, CN
• Qin Wang · Vancouver, CA
• Shibing Long · Beijing, CN

Key dates

• Filing date: Jun 30, 2011
• Grant date: Apr 22, 2014
• Expiry date: Dec 11, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/27

Abstract

The present disclosure relates to the field of microelectronics manufacture and memories. A three-dimensional multi-bit non-volatile memory and a method for manufacturing the same are disclosed. The memory comprises a plurality of memory cells constituting a memory array. The memory array may comprise: a gate stack structure; periodically and alternately arranged gate stack regions and channel region spaces; gate dielectric layers for discrete charge storage; periodically arranged channel regions; source doping regions and drain doping regions symmetrically arranged to each other; bit lines led from the source doping regions and the drain doping regions; and word lines led from the gate stack regions. The gate dielectric layers for discrete charge storage can provide physical storage spots to achieve single-bit or multi-bit operations, so as to achieve a high storage density. According to the present disclosure, the localized charge storage characteristic of the charge trapping layer and characteristics such as a longer effective channel length and a higher density of a vertical memory structure are utilized, to provide multiple storage spots in a single memory cell. Therefore, the…