Equalizer circuitry with selectable tap positions and coefficients
US8705602B1 · kind B1 · utility
6Cited by
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23Claims
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Key dates
| Filing date | Oct 16, 2009 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Oct 13, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03343
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Transmitter equalizer circuitry, e.g., for a serial, digital, data signal, includes tapped delay line circuitry for outputting a plurality of differently delayed versions of the signal propagating through the delay line circuitry. The equalizer circuitry also includes a plurality of electrical current digital-to-analog converters (“DACs”). The equalizer circuitry still further includes controllable (e.g., programmable) routing circuitry for selectably routing the delayed versions of the signal to the various DACs. The current strengths employed by the various DACs are also preferably controllable (e.g., programmable).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.