Digital signal processing circuit for generating output signal according to non-overlapping clock signals and input bit streams and related wireless communication transmitters
US8705657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2011 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Oct 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/3427
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital signal processing circuit includes a combining stage and an output stage. The combining stage is arranged to receive a plurality of non-overlapping clock signals having a same frequency but different phases, receive a plurality of first input bit streams, and generate a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals. The output stage is arranged to generate an output according to the first output bit stream. A digital signal processing method includes: receiving a plurality of non-overlapping clock signals having a same frequency but different phases; receiving a plurality of first input bit streams; generating a first output bit stream by combining the first input bit streams according to the non-overlapping clock signals; and generating an output according to the first output bit stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.