Method and apparatus for clock recovery in XDSL transceivers
US8705676B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2010 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Jul 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2676
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multi-tone transceiver including: a transform component, a tone selector, an error detector, an aggregator and an oscillator. The transform component transforms received communications from the time domain to the frequency domain. The tone selector selects a sub-set of the received tones which exhibit an elevated signal-to-noise ratio (SNR) as a clock recovery tone set (CRTS) and drops and add tones to the CRTS as required by changes in the SNR of the individual tones. The error detector detects phase errors in each received tone of the CRTS. The aggregator calculates an average aggregate phase error from all tones in the CRTS. The oscillator controls clocking of the transceiver. The oscillator is responsive to the average aggregate phase error to adjust a clock phase in a direction which reduces a phase error with a clock on the opposing transceiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.