CDR circuit
US8705680B2 · kind B2 · utility
1Cited by
13References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2007 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Aug 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A recovered clock (123) is generated by making the phase of a reference clock (122) having the same frequency as the data rate frequency of input data (120) match the phase of the input data (120). The input data (120) is written in a FIFO (101) using the recovered clock (123). For readout from the FIFO (101), the FIFO (101) is caused to output recovered data (121) using the reference clock (122) asynchronous to the recovered clock (123).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.