Accelerating memory operations blocked by ordering requirements and data not yet received
US8706925B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2011 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Apr 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller, system, and method for accelerating blocking memory operations. A memory controller reorders memory operations so as to maximize efficient use of the memory device bus. When data for a newer memory operation is retrieved from memory and ready to be returned to a source device, the newer memory operation can be held up waiting for an older memory operation to be completed. In response, the memory controller forwards a push request for the older memory operation to a memory channel unit. The memory channel unit then sets a push bit of the older memory operation, which expedites the scheduling of the older memory operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.