Method and system of debugging multicore bus transaction problems
US8706937B2 · kind B2 · utility
2Cited by
4References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 17, 2011 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Mar 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.