Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines
US8707127B2 · kind B2 · utility
2Cited by
3References
4Claims
0Family size
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Key dates
| Filing date | Sep 23, 2011 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Jan 22, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.