Integrated circuit routing with compaction
US8707239B2 · kind B2 · utility
4Cited by
70References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 11, 2012 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | Dec 11, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying solid and hollow channels, the technique automatically places route paths to connect pins of cells in the solid channels, where route paths may be placed within the solid channels or hollow channels. The technique can reduce a width of at least one hollow channel when an entire space of the hollow channel is not occupied by a placed route path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.