Method of forming a semiconductor package
US8709879B2 · kind B2 · utility
3Cited by
11References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Mar 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.