Semiconductor memory device and manufacturing method thereof
US8709889B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 2012 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Oct 11, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02631
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell therein includes a first transistor and a capacitor and stores data corresponding to a potential held in the capacitor. The first transistor includes a pair of electrodes, an insulating film in contact with side surfaces of the electrodes, a first gate electrode provided between the electrodes with the insulating film provided between the first gate electrode and each electrode and whose top surface is at a lower level than top surfaces of the electrodes, a first gate insulating film over the first gate electrode, an oxide semiconductor film in contact with the first gate insulating film and the electrodes, a second gate insulating film at least over the oxide semiconductor film, and a second gate electrode over the oxide semiconductor film with the second gate insulating film provided therebetween. The capacitor is connected to the first transistor through one of the electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.