Latch-up free ESD protection
US8710545B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2012 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Oct 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D18/251
Abstract
An ESD module having a first portion (FP) and a second portion (SP) in a substrate is presented. The FP includes a FP well of a second polarity type and first and second FP contact regions. The first FP contact region is of a first polarity type and the second FP contact region is of a second polarity type. The SP includes a SP well of a first polarity type and first and second SP contact regions. The first SP contact region is of a first polarity type and the second SP contact region is of a second polarity type. An intermediate portion (IP) is disposed in the substrate between the FP and SP in the substrate. The IP includes a well of the second polarity type. The IP increases trigger current and holding voltage of the module to prevent latch up during normal device operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.