Patent · US Active

Semiconductor arrangement with a solder resist layer

US8710609B2 · kind B2 · utility

2Cited by

4References

13Claims

0Family size

Assignee

OSRAM Opto Semiconductors GmbH · DE

Inventors

Michael Zitzlsperger · Regensburg, DE
Matthias Sperl · Mintraching, DE

Key dates

Filing date	Jan 29, 2010
Grant date	Apr 29, 2014
Priority date	—
Expiry date	Jan 29, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH10H20/853
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor arrangement including at least one lead arrangement with a top and a bottom opposite the top; at least one solder resist layer which partially covers the top and the bottom, at least sub-zones of the top and the bottom, which are not covered by the solder resist layer, forming electrical base members; an optoelectronic semiconductor element, which is mounted on at least one of the base members on the top of the lead arrangement and is connected electrically conductively therewith, and an encapsulant applied at least to the top of the lead arrangement, the encapsulant covering up the semiconductor element and lying at least partially against the solder resist layer, wherein the base members are bordered all round by the solder resist layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.