Semiconductor device and manufacturing method thereof
US8710619B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2011 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Oct 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To provide, in a semiconductor device formed on an SOI substrate and having a semiconductor layer of the SOI substrate surrounded, at the periphery of the element region thereof, with element isolation, a technology capable of preventing reliability deterioration attributed to the element isolation. Appearance of a hollow, which is formed upon filling of a deep trench with an insulating film, from the upper surface of the insulating film can be prevented by setting the trench width of the upper portion of the deep trench configuring trench isolation at less than 1.2 μm. Reduction in the breakdown voltage between adjacent element regions which may presumably occur due to a decrease in the trench width of the upper portion of the deep trench can be prevented by forming, on the upper portion of the deep trench, an LOCOS insulating film coupled to the insulating film filled in the deep trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.