Switched capacitor hold-up scheme for constant boost output voltage
US8710820B2 · kind B2 · utility
19Cited by
18References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2010 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Dec 29, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power architecture receives an input signal at an input node and converts the input signal into an intermediate signal with a power conversion stage. The power conversion stage supplies the intermediate signal to an output node of the power conversion stage where the intermediate signal is filtered with an operating capacitance coupled to the output node. A hold-up capacitance is charged, and when a loss of the input signal is detected, the hold-up capacitance is coupled to the input node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.