Dynamically reconfigurable systolic array accelorators
US8710864B2 · kind B2 · utility
4Cited by
1References
14Claims
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Key dates
| Filing date | Apr 22, 2011 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Oct 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms and extendable to more complex applications in the area of aerospace embedded systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.