Inverter, NAND gate, and NOR gate
US8710866B2 · kind B2 · utility
1Cited by
3References
7Claims
0Family size
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Key dates
| Filing date | Oct 9, 2013 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Oct 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.