MOS resistor apparatus and methods
US8710904B2 · kind B2 · utility
4Cited by
1References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2012 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Dec 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/245
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods disclosed herein implement a MOS resistor using the current channel of a MOS transistor. The MOS resistance R(DS) is dependent upon MOS transistor geometry and nominal gate voltage. MOS resistor terminal-to-gate voltages are averaged and applied to the MOS transistor gate such as to maintain the MOS resistor terminal voltage to current ratio, resulting in a substantially constant R(DS). R(DS) is also compensated for temperature and process variations by adjusting gate voltages via negative feedback methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.