Categorizing bit errors of solid-state, non-volatile memory
US8711619B2 · kind B2 · utility
10Cited by
27References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 18, 2011 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Jul 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bit errors affecting cells of a solid-state, non-volatile memory are assigned to at least a first or a second category based on a relative amount of voltage shift that caused the respective bit errors in the respective cells. A reference voltage used to access the respective cells is adjusted to manage the respective bit errors of the first category. Additional corrective measures are taken to manage the respective bit errors of the second category.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.