Memory device and self interleaving method thereof
US8711624B2 · kind B2 · utility
9Cited by
3References
42Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2011 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Jan 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.