Memory device, test operation method thereof, and system including the same
US8711641B2 · kind B2 · utility
8Cited by
3References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 21, 2011 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Jun 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test operation method of a memory device includes a reference current generator generating a reference current and providing a reference voltage generated based on the reference current to one of input terminals of a sense amplifier; providing a read voltage generated based on a read current of a memory cell to another one of the input terminals of the sense amplifier; and the sense amplifier comparing the reference voltage with the read voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.