Circuit for compressing data and a processor employing same
US8713080B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2008 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Aug 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application addresses a fundamental problem in the design of computing systems, that of minimizing the cost of memory access. This is a fundamental limitation on the design of computer systems as regardless of the memory technology or manner of connection to the processor, there is a maximum limitation on how much data can be transferred between processor and memory in a given time, this is the available memory bandwidth and the limitation of compute power by available memory bandwidth is often referred to as the memory-wall. The solution provided creates a map of a data structure to be compressed, the map representing the locations of non-trivial data values in the structure (e.g. non-zero values) and deleting the trivial data values from the structure to provide a compressed structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.