Processor and data transfer method
US8713216B2 · kind B2 · utility
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17References
8Claims
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Key dates
| Filing date | Jul 16, 2010 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | May 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor. In response to requests from a processing section, first and second memory controllers transfer first and second data items to the processing section via first and second buses, respectively. When transfers of the data items are concurrently performed via the first and second buses, one of the data items is transferred to the processing section by the buffer controller, and the other of the data items is stored in the buffer by the buffer controller. Then, after termination of transfer of the one of the data items, the other data item is transferred from the buffer to the processing section by the buffer controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.