Memory device and method for dynamic random access memory having serial interface and integral instruction buffer
US8713248B2 · kind B2 · utility
1Cited by
4References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 2, 2009 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Apr 1, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory integrated circuit includes an interface to a serial interconnect, where the interface is configured to receive a plurality of memory access instructions over the serial interconnect, and a buffer configured to store the plurality of memory access instructions prior to execution of the buffered memory access instructions by the dynamic random access memory integrated circuit. The memory access instructions are received over at least one serial link that forms the serial interconnect, and the at least one serial link may be a shared bi-directional serial link or a uni-directional serial link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.