Cache memory control device, semiconductor integrated circuit, and cache memory control method
US8713291B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 2010 |
| Grant date | Apr 29, 2014 |
| Priority date | — |
| Expiry date | Oct 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory control device includes cache memories shared by arithmetic processing units, buses shared by the arithmetic processing units to transfer data, an instruction execution unit that accesses the cache memories to execute an access instruction from the arithmetic processing unit, and transfers data from the cache memory to the bus, an instruction feeding unit that feeds the access instruction to the instruction execution unit while inhibiting feeding of a subsequent access instruction for the cache memory accessed in the preceding access instruction in an execution period of the preceding access instruction and inhibiting feeding of a subsequent access instruction using the same bus as the preceding access instruction in a predetermined period, and a timing control unit that, depending on the type of the subsequent access instruction, controls the instruction executing unit to delay the transfer of the data from the cache memory to the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.